`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   01:34:32 05/05/2013
// Design Name:   CPU
// Module Name:   F:/320current/CSE 320/VLab3/CSE 320n/Vlab2/FIFO1/tb_CPU.v
// Project Name:  FIFO1
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: CPU
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_CPU;

	// Inputs
	reg inst_ex;
	reg [7:0] inst_data;
	reg reset_b;
	reg clk_50Mhz;
	reg reg_read;

	// Outputs
	wire [15:0] reg_data;

	// Instantiate the Unit Under Test (UUT)
	CPU uut (
		.inst_ex(inst_ex), 
		.inst_data(inst_data), 
		.reset_b(reset_b), 
		.clk_50Mhz(clk_50Mhz), 
		.reg_read(reg_read), 
		.reg_data(reg_data)
	);

	initial begin
		forever #10 clk_50Mhz <= ~clk_50Mhz;
	end 
	
	initial begin
		// Initialize Inputs
		inst_ex = 0;
		inst_data = 0;
		reset_b = 1;
		clk_50Mhz = 0;
		reg_read = 0;

		//Load
		#30 inst_ex = 1'b1; inst_data = 8'b11110000;
		#20 inst_ex = 1'b0; 
		#20 inst_ex = 1'b1; inst_data = 8'b10000100;
		#30 inst_ex = 1'b0;
		#20 inst_ex = 1'b1; inst_data = 8'b01011000; 
		#20 inst_ex = 1'b0;
		#20 inst_ex = 1'b1; inst_data = 8'b00111100;
		#20 inst_ex = 1'b0;
		
		//
		#20 inst_ex = 1'b1; inst_data = 8'b01101101; //Sum A and C put int D
		#20 inst_ex = 1'b0;
		
		#10 reg_read = 1'b1;

	end
      
endmodule


